Avalon MM master templete (Avalon master 예제)

The templates provided contain Avalon^® Memory-Mapped (MM) Verilog modules bundled as an SOPC Builder-ready component. The component is capable of accessing memory and exposes a simple interface you can access with your own custom logic. The component is parameterizable, allowing you to trade off functionality for area and performance optimizations. You can use the components with any Altera^® device family supported by SOPC Builder. The component is Verilog based, so you can add your own custom logic to create a self-contained component. Simply use the component editor available in SOPC Builder to create a new component based on the master template Verilog file and your own source file(s). For ease of use, the component uses Tcl callbacks to allow you to make setting changes automatically in a GUI environment.

The system interconnect fabric supports bursting and non-bursting transfers, so various specialized components are provided. Select the component settings that are most appropriate for the memory types in your system to avoid generating excessive logic. Table 1 outlines which component to use, based on your system requirements.

출처 :

https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html