Avalon bus의 기초 read, write 동작

The numbers in this timing diagram, mark the following transitions:

1. address, byteenable, and read are asserted after the rising edge of clk.
    The slave asserts waitrequest, stalling the transfer.
2. waitrequest is sampled. Because waitrequest is asserted, the cycle becomes a wait-state. 
    Address,read, write, and byteenable remain constant.
3. The slave deasserts waitrequest after the rising edge of clk.
4. readdata, response and deasserted waitrequest are sampled, completing the transfer.
5. address, writedata, byteenable, and write signals are asserted after the rising edge of clk.
    The slave asserts waitrequest stalling the transfer.
6. The slave deasserts waitrequest after the rising edge of clk.
7. The slave captures write data ending the transfer.

--> 요약하자면...
      master에서 slave로 read 시 'read' signal을 올려주면, default low에 있던 "waitrequest"가
      응답(slave 응답)하여 "high"가 되고, read address를 latch하여 "readdatavalid"구간에 data를 master에게
      넘겨 준다.
      
      반대로, master에서 slave write 시 'write' signal을 올려주면, default low에 있던 "waitrequest"가 응답
      (slave 응답)하여 "high"가 되고, slave의 address에 write 동작을 진행한다.