You may see the above error when the PLL reference clock input to the UniPHY-based memory controller is fed from another PLL. While it is not recommended to cascade PLLs, it is allowed and the design should compile with warnings but no errors.
The cause of the above error is that the number of hierarchical levels for the reference clock has exceeded the value in the <variation_name>_p0_get_input_clk_id procedure in the <variation_name>_p0_pin_map.tcl file.