1. Target device : Cyclone V SoC 2. External Memory : DDR3 1Gb The design leverages the ability for users to send Avalon® Memory Mapped commands over JTAG. The Avalon-MM commands are routed to a JTAG to Avalon Master Bridge, which is tied to the FPGA To HPS AXI™ Bridge on the HPS. From there the data is directed into the L3 Interconnect where it is routed based on the dest..