UART bit stream 구조

 

 

Data Transmission

It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register. The transmitter can also produce the break condition, which forces the serial output to logic 0 state for one frame transmission time. This block transmits break signals after the present transmission word is transmitted completely. After the break signal transmission, it continuously transmits data into the Tx FIFO.

 

Data Reception

Like the transmission, it consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits in the line control register. The receiver can detect overrun error, parity error, frame error and break condition, each of which can set an error flag.

   - The overrun error indicates that new data has overwritten the old data before the old data has been read.
   - The parity error indicates that the receiver has detected an unexpected parity condition.
   - The frame error indicates that the received data does not have a valid stop bit.
   - The break condition indicates that the RX input is held in the logic 0 state for a duration longer than one frame transmission time