7:1 LVDS Interface Requirement

 

7:1 LVDS Interface Requirement

 

The 7:1 LVDS interface is a source synchronous LVDS interface. Seven data bits are serialized for each cycle of
the low-speed clock as shown in Figure 1. Typically, the interface consists of four (three data, one clock) or five (four
data, one clock) LVDS pairs. The four pairs translate to 21 parallel data bits and five pairs translate to 28 parallel
data bits. Note that there is a 2-bit offset between the clock rising edge and the word boundary. Each word is 7 bits
long.

 

 

 

Each channel includes a serial LVDS data pair along with a source synchronous LVDS clock pair. The receiver
receives this serial LVDS data, deserializes it and aligns it to the original word boundary to generate seven parallel
LVTTL data bits. The 7:1 transmitter serializes the seven LVTTL parallel data bits to a single LVDS data bit and
transmits this serial data channel along with a LVDS clock.

Figure 2 shows the 7:1 receiver receiving four LVDS data channels. When deserialized, it generates 28-bit wide
parallel data. Similarly, the 7:1 transmitter serializes 28-bit parallel data to generate four LVDS data channels.

 

 

The requirements for an FPGA-based solution to the Channel Link and Flat Link style interfaces consist of four key
components: high-speed LVDS buffers, a PLL for generating the de-serialization clock, input data capture and
gearing, and data formatting.

The data and clock are received or transmitted to or from the FPGA in LVDS format, with the data at relatively high
speed. The exact speed depends on the resolution, frame rate and color depth used by the display. For example,
800x600 to 1024x768 displays require LVDS data to be transmitted from 40 MHz to 78.5 MHz for 60 Hz to 75 Hz
refresh rates. This translates to LVDS data rates of 280 Mbps to 549 Mbps. Higher resolution displays, such as
1280x1024 60 Hz, require data to be transmitted with 108 MHz LVDS clocks. For this system, data will transmit at
756 Mbps.

 

Clock Generation
In a LatticeECP3, LatticeECP2/M or LatticeXP2 implementation, the input capture circuitry uses Double Data Rate
(DDR) registers with data captured on both the rising and falling edges of the clock. When operating as a receiver
the low-speed clock that is provided with the data must be multiplied by 3.5 times in order to capture the data on
both clock edges. If the input capture circuitry operates on only one edge of the clock, a multiplication factor of
seven must be used. As an alternative, seven phase-shifted versions of the low-speed clock can be generated and
used to capture the input data with seven different registers. However, the challenges of clock generation and distribution
discourage this approach for an FPGA implementation. The clock must have relatively low jitter since its jitter
must be accounted for in the overall timing budget. Similarly, the skew of the clock distribution network used to provide
this clock to input or output registers must be accounted for in any timing analysis.

In order to transmit high-speed data, a transmitter must multiply the clock used to transfer low-speed parallel data
into the interface by 3.5. Again, the jitter of the clock and the skew of its distribution are important as they impact
the timing budget for the interface. Figure 3 shows the PLL clock generation and how the R, G, B bits, Vsync,
Hsync, and DE of a pixel on line 2 of a video frame get assigned to the four LVDS data pairs. The data bits are sampled
on both rising and falling edges of the eclk clock.