Round-robin Arbiter Design and Generation

 

ABSTRACT
In this paper, we introduce a Round–robin Arbiter Generator (RAG) tool. The RAG tool can generate a design

for a Bus Arbiter (BA).
The BA is able to handle the exact number of bus masters for both on-chip and off-chip buses.

RAG can also generate a distributed and parallel hierarchical Switch Arbiter (SA).

The first contribution of this paper is the automated generation of a round-robin token passing BA to reduce time

spent on arbiter design. The generated arbiter is fair, fast, and has a low and predictable worst-case wait time.

The second contribution of this paper is the design and integration of a distributed fast arbiter, e.g., for a terabit switch,
based on 2x2 and 4x4 switch arbiters (SAs). Using a .25μ TSMC standard cell library from LEDA Systems [10, 14],

we show the arbitration time of a 256x256 SA for a terabit switch and demonstrate that the SA generated by

RAG meets the time constraint to achieve approximately six terabits of throughput in a typical network switch design.

Furthermore, our generated SA performs better than the Ping-Pong Arbiter and Programmable Priority Encoder by a factor of 1.9X and 2.4X, respectively.

 

 

 

Verilog Round Robin Arbiter Model.pdf

Verilog Round Robin Arbiter Model.pdf

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