[gennum] AVIIA - GV7600 or GV7601 Debugging Point

 

 

1. GV7600 or GV7601 does not work at all

Check
1) All power supply voltages
   The voltage on VCO_VDD pin is about 0.7~0.8V.

   The serial resistor should be 105 ohm (or you can use 100 ohm), not 1M (10x105) ohm.

2) Is there a 1ms low pulse on RESETb pin after power on? After that, is RESETb high?

3) Is STANDBY pin low?

4) Is JTAG_EN pin low?

5) Are GV7600 D5, F7, H8 pins connected to GND?

 

 

2. Powers are right, still no video

Check
1) Use a scope to watch LOCKED, not just use multimeter or see LED.
    LOCKED is very important status signal. It indicates the PLL locking status.

    A stably high LOCKED signal is the basic starter to debug your board.

2) GV7600: High LOCKED means PLL locks to the PCLK only. 
    If LOCKED is not stably high,
    - Check your input video stream rate (SD, HD or 3G)

    - Measure your PCLK, is it one of frequencies 13.5, 27, 74.25, 148.5MHz?
    - Check your RATE_SEL[1:0] pins setting. RATE_SEL[1:0] = x1, 00, 10 for SD, HD, 3G respectively.
    - Check 20BIT/10BITb pin, is it proper to your data bus width? 

3) GV7601: High LOCKED means PLL locks to serial input AND the video format is detected.
   If LOCKED is not stably high,
   - Check the SDI input circuit, are the right components installed? 
   - Measure the noise Vpp on 1.2V, 3.3V and GND. Is it too high (such as over 200mVpp)?
   - Is GV7601 working at manual mode (bit 2 of 0x024h=0)? Are RAET_SEL bits set correctly?
   - Is the GV7601 loop-through output good to receive?
   - Do you ever check your SDI source with another verified receiver?

4) While GV7601 works at auto mode (default) and LOCKED is low,
   PCLK pin will cycle output 13.5/27M, 74.25M and 148.5MHz clock. This is normal.
The PLL is looping its state machine to try locking to the SDI input.

 

 

3. LOCKED is high, still no video
Check

GV7600:
 1) Is the input video timing (DETECT_TRS, 861_EN) set correctly?

 2) Are the configuration pins (PROC_EN=1, 656_BYPASSb=1, SDO_EN=1, ASI=0) set correctly?

 3) Measure H/V/F(DE) frequencies and pulse width, are they correct?

 4) Read register 0x001, 004, 012~015h. Does GV7600 detect the video format correctly?

 5) If using CEA-861 timing,
    - not all video formats are supported;
    - the input timing H/V/DE must be exactly same as CEA-861 timing.

GV7601:
1) Is the output video timing (861_EN) set correctly to meet the back-end chip?

2) Measure H/V/F(DE) frequencies and pulse width, are they correct?
    If not, is your input SDI signal a standard video format? Does your back-end chip support this format?

3) Are the configuration pins (PROC_EN=1) set correctly?

4) (scope) Watch DATA_ERRORb pin (STAT5), is it low most of time?

5) Read register 0x002, 006, 01F~026h. Does GV7601 detect the video format correctly?

    Read them several times, are the values stable?
    If using CEA-861 timing, not all video formats are supported.

 

4. I got the video, but with noise lines/points or flickering

Check
GV7600:
 1) Read register 0x001, 004, 012~015h several times, are the values stable?

 2) Measure noises on 3.3V/1.2V and GND. If over 100mVpp, add caps to reduce it.

 3) Reduce the PLL bandwidth by reducing R1 to 200 or 100 ohm, increasing C2 a little for stability.

 4) Watch the input PCLK and parallel data bus,adjust their edges and ringing by tuning the series resistor value or

    source driving strength. 
  

GV7601:
 1) (scope) Watch DATA_ERRORb pin (STAT5), are there many low pulses?

 2) Read register 0x002, 006, 01F~023h several times, are the values stable?

 3) Measure noises on 3.3V/1.2V and GND. If over 100mVpp, add caps to reduce it.

 4) Watch GV7601 output PCLK and parallel data bus, adjust their edges and ringing by tuning the series resistor value,
you can adjust driving strength by register 0x06Dh.

 

 

5. GV7600 serial output has big jitters.

Check

1) If its alignment jitter is high (>0.2UI), check the noises on powers; reduce the GV7600 PLL bandwidth.

2) Often see big timing jitter.

3) Roughly watch your PCLK jitters

4) Check your front-end chip
   - Use more accurate crystal/oscillator
   - Is there SSC feature? Disable it.
   - Lower down its data bus and PCLK driving strength

5) Adjust series resistors on parallel data bus and PCLK, the transition edges are not too steap.

6) Add RC filter on PCLK, 
    R= 100 or above,  C= xx pF

 

 

6. Eye Pattern

Check

1) Rset resistor value adjusts the eye amplitude.
   - Rset = 750 ohm, SDO output swing is 800mV with 75-ohm load.
   - Bigger Rset, smaller swing

 

2) Inductor in output return loss compensation network can adjust the rising/falling edge steepness. Inductor range is 3.3~6.8nH.
   - Smaller inductor value, steeper edges, but the return loss will be worse

 

    

                          5.6nH inductor                                                      3.9nH inductor

 3) If the eye still looks ugly, temporarily remove the ESD component and back-channel filter beads first.

 

 

7. Audio

Check

 1) I can not get audio from GV7600 output. 
     - Is its video output correct?
     - Check configuration pins PROC_EN, GRP1/2_EN
     - Is the input audio stream 48KHz sampling rate? Measure WCLK, ACLK
     - Is the input audio format as same as you set at reg 0x40Bh (SD) or reg 0x80Ah (HD)?    
     - SD or HD video format? If SD, are you A/V synced before feeding to GV7600?

 2) I can not get audio from GV7601 output. 
     - Is its video output correct?
     - Check configuration pins PROC_EN and AUDIO_EN
     - Is the output audio format set correctly? 
     - Measure WCLK, ACLK. Are they correct?
     - Is the input SDI stream verified by a verified receiver?
     - Read reg 0x401h/403h/404h/406h (SD), reg 0x201h/202h/203h/206h/209h (HD). Does the input stream have the audio in Group 1?

 3) My GV7601 output audio has noises. 
     - Is the input SDI stream verified by a verified receiver?
     - If it’s HD video, set bit 5 of reg 0x208h to 1. 

 

 

8. What I need to measure?

Check
 1) Different video formats as your system specification
 2) Eye pattern – amplitude, rising/falling time, overshoot (to GV7600 and GV8500)
 3) Jitters - alignment jitter and timing jitter (to GV7600 and GV8500)
 4) Cable length while without data error (to receiver design)
 5) Return loss
 6) CRC errors